1. Field of the Invention
The present invention relates to a random access memory using complementary field effect devices. More specifically, the present invention relates to a static type random access memory implemented by complementary field effect transistors.
2. Description of the Prior Art
As well known, a random access memory comprises an array of a plurality of storing cells, address signal lines associated with said plurality of storing cells for addressing the said plurality of storing cells, and a data signal line commonly connected to the said plurality of storing cells for inputting/outputting a data signal. Of late, a typical random access memory is implemented by field effect devices. Some type of a random access memory may be implemented by complementary field effect devices.
FIG. 1 shows a schematic diagram of a typical prior art static type random access memory implemented by complementary field effect transistors. Referring to FIG. 1, each field effect transistor is shown by a well known symbol. As well known, complementary field effect transistors comprise a pair of field effect transistors which are different from each other or opposite to each other in terms of the conductivity type. Typically, the complementary field effect transistors comprise a pair of a P channel enhancement field effect transistor and an N channel enhancement field effect transistor. In the figure, a P channel enhancement field effect transistor is denoted by the reference character P indicated adjacent the symbol of the field effect transistor and an N channel enhancement field effect transistor is denoted by the reference character N indicated adjacent the symbol of the field effect transistor. It is pointed out that FIG. 1 shows only one storing cell, and an address signal line and data signal line to be connected thereto. The figure only shows a row address signal line, while a column address signal line is omitted.
Referring to FIG. 1, the circuit is shown connected between the voltage source +VDD and the ground GND. It is pointed out that, as far as the description in conjunction with FIG. 1 is concerned, the logical convention is adopted wherein the voltage level of the voltage source +VDD is handled as true or the logic one or the high level while the voltage level of the ground GND is handled as false or the logic zero or the low level.
The circuit diagram in FIG. 1 comprises one storing cell, as described above, which is implemented by a pair of inverters, one comprising a P channel enhancement field effect transistor T3 and an N channel enhancement field effect transistor T5 and the other comprising a P channel enhancement field effect transistor T3' and an N channel enhancement field effect transistor T5', and a pair of transmission gates, one comprising an N channel enhancement field effect transistor T2 and the other comprising an N channel enhancement field effect transistor T2'. The junction between the field effect transistors T3 and T5 is connected to the gate electrodes of the field effect transistors T3' and T5', while the junction between the field effect transistors T3' and T5' is connected to the gate electrodes of the field effect transistors T3 and T5, whereby a cross connection of the pair of inverters is implemented to form a flip-flop, which serves as a storing cell. A data signal line of the circuit shown comprises a pair of data signal lines L2 and L2' which are complementary to each other in terms of the logic. The field effect transistor T2 serving as a transmission gate is connected between the junction of the field effect transistor T3 and T5 and the data signal line L2, while the field effect transistor T2' serving as a transmission gate is connected between the junction of the field effect transistors T3' and T5' and the data signal line L2'. The gate electrodes of the field effect transistors T2 annd T2' are connected to an address signal line L1 which is to be used as a row address signal line. The data signal lines L2 and L2' are connected through P channel enhancement field effect transistors T4 and T4', respectively, to the voltage source +VDD. The gate electrodes of the field effect transistors T4 and T4' are grounded so that the transistors T4 and T4' are normally conductive and serve as resistors. The data signal line L2 is connected through an N channel enhancement field effect transistor T1 to the ground GND. The gate electrode of the field effect transistor T1 constitutes a data input signal line DIN. Similarly, the data signal line L2' is connected through an N channel enhancement field effect transistor T1' to the ground GND. The gate electrode of the field effect transistor T1' constitutes another data input signal line DIN'.
First consider a read operation mode of the FIG. 1 diagram. To that end, let it be assumed that the address signal line L1 is selected or addressed, namely the address signal line L1 is brought to the voltage level of the voltage source +VDD or to the logic one. As a result, the field effect transistors T2 and T2' become conductive. Therefore, the storing state of the flip-flop is outputted to the data signal lines L2 and L2' by way of the output signals DOUT and DOUT which are complementary. Consider a storing state in the flip-flop in more detail. By way of an example, assuming that the field effect transistors T3' and T5 are turned on and the field effect transistors T3 and T5' are turned off, the junction between the transistors T3' and T5' becomes the high level or true, which is outputted through the data signal line L2', while the junction between the transistors T3 and T5 becomes the low level or false which is outputted through the data signal line L2. The high level at the junction between the transistors T3' and T5' causes the transistor T3 to be turned off and the transistor T5 to be turned on, while the low level at the junction between the transistors T3 and T5 causes the transistor T3' to be turned on and the transistor T5' to be turned off, whereby the above described storing state of the flip-flop is established. Assuming the reverse conduction state in each transistor, then the reverse storing state is established in the flip-flop and the corresponding data output is obtained in each of the data signal lines L2 and L2'. It is pointed out that, although not shown in FIG. 1 the data input signal lines DIN and DIN' are both adapted to be brought to the low level so that the transistors T1 and T1' are turned off in the read operation mode.
Now consider a write operation mode. To that end, again let it be assumed that the address signal line L1 is selected or addressed, so that the address signal line L1 is brought to the high level or the logic one. Therefore the transistors T2 and T2' are turned on and accordingly the storing cell implemented by the transistors T3, T5, T3' and T5' is addressed or selected. Assuming further that the input data signal DIN is the logic one and the data input signal DIN' is the logic zero, then the field effect transistor T1 is turned on while the field effect transistor T1' is turned off. As a result, the data signal line L2 is forced to the voltage level of the ground GND or to the low level, while the data signal line L2' is brought to the voltage level of the voltage source +VDD or to the high level. The voltage levels in these data signal lines L2 and L2' are applied through the transmission gates T2 and T2' to the flip-flop as an input data signal of the logic one, whereby the corresponding storing state is established in the flip-flop.
It has been observed that a problem is encountered with the FIG. 1 random access memory in the read operation mode. For the purpose of considering such a problem, let it be assumed that a storing state has been established in the flip-flop wherein the field effect transistors T3 and T5' are turned on and the field effect transistors T3' and T5 are turned off, whereby the junction between the transistors T3 and T5 is the high level and the junction between the transistors T3' and T5' is the low level. Before the field effect transistors T2 and T2' are turned on, the data signal lines L2 and L2' are in the voltage level of the voltage source +VDD. If and when the address signal line L1 is brought to the high level for the purpose of addressing the storing cell in the read operation mode and the field effect transistors T2 and T2' are turned on, then the high level potential at the junction between the transistors T3 and T5 is coupled to the data signal line L2 which is the high level at that time, while the low level at the junction between the transistors T3' and T5' is coupled to the data signal line L2' which is also the high level, with the result that the high level at the data signal line L2' must be forced to the low level. Such a change of the voltage level at the data signal line L2' is effected by conduction through the field effect transistors T2' and T5' to the ground GND. However, a direct current path is formed from the voltage source +VDD through the field effect transistors T4', T2' and T5' now in conduction to the ground GND. Assuming that the resistance across the field effect transistor T5' is large, then the voltage level at the junction between the transistors T3' and T5' approaches the voltage level of the voltage source +VDD, with the result of fear that the data stored in the storing cell is destroyed. Thus, from the standpoint of the read operation mode, the resistance across the field effect transistor T5' must be smaller. Assuming a reverse storing state of the flip-flop, then the resistance of the field effect transistor T5 must also be smaller.
With the FIG. 1 random access memory, another problem is encountered in the write operation mode. For the purpose of considering the problem, again assume a storing state in the flip-flop wherein the field effect transistors T3 and T5' are turned on while the field effect transistors T3' and T5 are turned off, whereby the junction between the transistors T3 and T5 is the high level while the junction between the transistors T3' and T5' is the low level. No problem occurs when the same data input signal as the storing state of the flip-flop is applied to the flip-flop and no change of the storing state occurs in the flip-flop. However, a problem occurs in conjunction with the change of the storing state in the flip-flop as a result of the writing operation in the flip-flop. Now consider a case where inversion of the storing state occurs in the flip-flop. Then, the high level at the junction between the transistors T3 and T5 must be forced to the low level. To that end, the logic one or the high level signal is applied to the data input signal line DIN and the logic zero or the low level signal is applied to the data input signal line DIN'. As a result, the field effect transistor T1 is turned on. In such a situation, a direct current path is formed between the voltage source +VDD and the ground GND through the transistors T1, T2, and T3 now in conduction. In such a situation, the resistance of the transistor T1 must be sufficiently small enough to fully force the potential at the junction between the transistors T3 and T5 to the ground through the transistors T2 and T1. Considering a reverse state, the resistance of the transistor T1' also must be sufficiently small. Considering the transistors T1 and T3', the resistance of the transistors T3 and T3' must be sufficiently larger than the resistance of both transistors T1 and T2, and both transistors T1' and T2', respectively. Considering further the transistors T4 and T4' normally in conduction, the resistance of the transistors T1 and T1' must be sufficiently small enough to allow a current to flow through both the transistors T4 and a series connection of the transistors T2 and T3 and both the transistor T4' and a series connection of the transistors T2' and T3', respectively.
In summary, with the FIG. 1 random access memory, the field effect transistors included therein must be ratioed as expressed as follows in terms of the resistance thereof.
T3 &gt; t2 + t1 PA1 t2 + t4 &gt; t5 PA1 t4 &gt; t1
the fact that the field effect transistors must be ratioed in designing the same causes an increase of the area, difficulty in designing and an increase in power dissipation, as well known to those skilled in the art.